Tl;dr: I’m writing a blog about making a MIPS CPU in Hardcaml. Hi! My name is Sasha, and I’m a student at Penn State majoring in CS and Math. Last semester, I took a computer engineering class where we built a pipelined MIPS CPU in Verilog as a semester-long project. I enjoyed the class, but a lot …

Hi, I just want to say it’s a great project. There doesn’t seem to be many resources on hardcaml so I look forward to reading the blog!

I’m glad the episode struck a chord, and I’m excited to see what comes of your experiment. Good luck!

Very cool - really enjoying the blog posts! If you have any questions, suggestions or feedback for Hardcaml, please do open issues on Github. And here’s a deal - if you can run a compiled program in the Hardcaml simulator, I’ll buy you and your colleague an Arty A7 board to run it on.

Thank you all for the kind words and support! This has been a fun project so far, and now that we’re starting to get comfortable with Hardcaml, I’m hoping to have more updates soon. [image] avsm: Can we convince you to have a go at a simple RISC-V CPU once you have MIPS working? :slight_smile: …

Nice blog posts! If you want an example of Hardcaml on Arty A7, do have a look at this example Regardless of whether you use the Arty A7, src/infrastructure/uart.ml contains some ~non-trivial code examples for state machines.

:+1: Does your website have an RSS feed?

It does now! https://ceramichacker.com/rss. Also https://ceramichacker.com/atom for Atom users. On a side note, we’ve published two more posts: Memory in Hardcaml Registers and Stateful Design More coming soon!

Hi everyone! We are excited to announce that we have completed this project and blog. Progress has been slow these past few months due to work, internships, and college, but we’ve now released v1.0.0 on GitHub . We also published posts on: Design patterns, conventions, and testing How the Always DS…

@askvortsov amazing project and nice read! By the way, you might be interested in this discussion about joining the forces to choose one common low-level IR instead of using Verilog as the intermediate representation . So far most interesting candidates were FIRRTL , CIRCT (LLVM/MLIR-based language an…

Hardcaml MIPS CPU Learning Project and Blog

Learning

avsm July 5, 2021, 3:31pm 3

This is a really wonderful series of blogs! Can we convince you to have a go at a simple RISC-V CPU once you have MIPS working?

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Hardcaml MIPS CPU Learning Project and Blog

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