Tl;dr: I’m writing a blog about making a MIPS CPU in Hardcaml.
Hi! My name is Sasha, and I’m a student at Penn State majoring in CS and Math. Last semester, I took a computer engineering class where we built a pipelined MIPS CPU in Verilog as a semester-long project. I enjoyed the class, but a lot of frustration came from Verilog itself.
A few months ago, I came across the Signals and Threads Programmable Hardware episode. I really liked the idea of Hardcaml: a library to write and test hardware designs in OCaml. Representing circuits as functions felt like a good abstraction, and I’ve been wanting to learn OCaml for a while.
So this summer, a friend and I are rewriting the Verilog MIPS CPU we made last semester into Hardcaml. We’re still working on the project, but have made some good progress and wanted to share it in case anyone finds it interesting / useful. If anyone wants to take a look, it’s up on GitHub.
Thank you all for the kind words and support! This has been a fun project so far, and now that we’re starting to get comfortable with Hardcaml, I’m hoping to have more updates soon.
That’s a great idea! Once we get the core parts in place, there’s a few things I’d like to improve/add to the basic version we made in class. For instance, we’re initially implementing instruction memory as a mux, which is simple but not that realistic. I’d like to play around with the Xilinx memory library and try to get it working with actual RAM. Rewriting this project into a RISC-V CPU could be a fun challenge!
Absolutely! We’ve been keeping track of some “Hardcaml observations” in each post. Once we’ve gotten a bit more comfortable with the library and ecosystem, we’ll try and distill that into something useful.
Wow, thanks! With the magic powers of Hardcaml behind us, it should be doable
Hi everyone! We are excited to announce that we have completed this project and blog. Progress has been slow these past few months due to work, internships, and college, but we’ve now released v1.0.0 on GitHub. We also published posts on:
Finally, we published a conclusion blog post, which wraps up some strengths/weaknesses of Hardcaml, as well as some takeaways on OCaml and blogging more generally.
Thank you to @andyman and @fyquah95 for building Hardcaml, and for helping us out on GitHub issues! We really appreciate your time and suggestions.
Overall, we’ve come to the conclusion that Hardcaml is a much better tool for hardware design than Verilog. This has been a great experience, and we walk away with a better understanding of hardware, functional programming, and technical writing.
Hi everyone! Last fall, we completed our original plan for this project, rewriting the verilog MIPS CPU we had designed for a class into Hardcaml. A few weeks later, we got an invite to video-meet with the Hardcaml team to talk about our experience. They even sent us actual Arty A-7 FPGAs so we could test out our simulation on real hardware!
Junior year ended up much busier than expected, and although we had gotten our code onto the FPGAs by January, we’ve only just now fully finished our project. Our blog now has 2 bonus installments:
Hardcaml MIPS and I/O. Here, we restructured our CPU so that programs can communicate with an external device using UART.
With these changes, our full design is now a simplified but realistic processor that can run meaningful programs.
Thank you very much to @andyman, @fyquah95, Ben Devlin, and the rest of the Jane Street FPGA team for creating Hardcaml, meeting with us, and answering our numerous questions throughout this process. Thank you also to @yaron_minsky and Jane Street for sending us the FPGAs to try out our code.
This has been an incredibly interesting, challenging, and rewarding journey. We hope that our blog posts and sample project are useful for learning Hardcaml in the future, and welcome any questions or comments.
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