Tl;dr: I’m writing a blog about making a MIPS CPU in Hardcaml.
Hi! My name is Sasha, and I’m a student at Penn State majoring in CS and Math. Last semester, I took a computer engineering class where we built a pipelined MIPS CPU in Verilog as a semester-long project. I enjoyed the class, but a lot of frustration came from Verilog itself.
A few months ago, I came across the Signals and Threads Programmable Hardware episode. I really liked the idea of Hardcaml: a library to write and test hardware designs in OCaml. Representing circuits as functions felt like a good abstraction, and I’ve been wanting to learn OCaml for a while.
So this summer, a friend and I are rewriting the Verilog MIPS CPU we made last semester into Hardcaml. We’re still working on the project, but have made some good progress and wanted to share it in case anyone finds it interesting / useful. If anyone wants to take a look, it’s up on GitHub.
We’ve written some blog posts about our project:
- Some more background on what we’re doing and why
- An ELI5 overview of how hardware, and pipelined CPUs in particular, work
- Another high-level overview of Verilog, hardware design, FPGAs, and why I think OCaml might be a great fit for hardware design
- How to set up a Hardcaml project, including testing and Verilog generation
- How to split Hardcaml circuits into multiple modules
There’s also a few more that we’ve written code for, but are still drafting blog posts about:
- How to work with memory in Hardcaml
- How to design stateful, sequential circuits in Hardcaml
- A safer design pattern for Hardcaml circuits
I’m new to both OCaml and blogging, and this has definitely been a fun experience so far! Would love to hear any feedback / comments.