Hi everyone! Last fall, we completed our original plan for this project, rewriting the verilog MIPS CPU we had designed for a class into Hardcaml. A few weeks later, we got an invite to video-meet with the Hardcaml team to talk about our experience. They even sent us actual Arty A-7 FPGAs so we could test out our simulation on real hardware!
Junior year ended up much busier than expected, and although we had gotten our code onto the FPGAs by January, we’ve only just now fully finished our project. Our blog now has 2 bonus installments:
- Running Hardcaml on an actual FPGA. Here, we lit up LEDs to display the output of a hardcoded program.
- Hardcaml MIPS and I/O. Here, we restructured our CPU so that programs can communicate with an external device using UART.
With these changes, our full design is now a simplified but realistic processor that can run meaningful programs.
Thank you very much to @andyman, @fyquah95, Ben Devlin, and the rest of the Jane Street FPGA team for creating Hardcaml, meeting with us, and answering our numerous questions throughout this process. Thank you also to @yaron_minsky and Jane Street for sending us the FPGAs to try out our code.
This has been an incredibly interesting, challenging, and rewarding journey. We hope that our blog posts and sample project are useful for learning Hardcaml in the future, and welcome any questions or comments.