Hi everyone! We are excited to announce that we have completed this project and blog. Progress has been slow these past few months due to work, internships, and college, but we’ve now released v1.0.0 on GitHub. We also published posts on:
- Design patterns, conventions, and testing
- How the Always DSL can be used to write safe “pseudo-imperative” code in Hardcaml
- Hardcaml’s testing and interactive simulation tools
- A recap of some interesting hardware/CPU features in our design
Finally, we published a conclusion blog post, which wraps up some strengths/weaknesses of Hardcaml, as well as some takeaways on OCaml and blogging more generally.
Thank you to @andyman and @fyquah95 for building Hardcaml, and for helping us out on GitHub issues! We really appreciate your time and suggestions.
Overall, we’ve come to the conclusion that Hardcaml is a much better tool for hardware design than Verilog. This has been a great experience, and we walk away with a better understanding of hardware, functional programming, and technical writing.